diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index c3a829d..1bc6c99 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -131,6 +131,11 @@
 	help
 	  Enable support for SPI on MPC8XX
 
+config MPC8XXX_SPI
+	bool "MPC8XXX SPI Driver"
+	help
+	  Enable support for SPI on the MPC8XXX PowerPC SoCs.
+
 config MT7621_SPI
 	bool "MediaTek MT7621 SPI driver"
 	depends on SOC_MT7628
@@ -364,11 +369,6 @@
 	help
 	  Enable support for SPI on LPC32xx
 
-config MPC8XXX_SPI
-	bool "MPC8XXX SPI Driver"
-	help
-	  Enable support for SPI on the MPC8XXX PowerPC SoCs.
-
 config MXC_SPI
 	bool "MXC SPI Driver"
 	help
diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c
index 63e1a15..1c7bf10 100644
--- a/drivers/spi/mpc8xxx_spi.c
+++ b/drivers/spi/mpc8xxx_spi.c
@@ -5,10 +5,12 @@
  */
 
 #include <common.h>
-
+#include <dm.h>
+#include <errno.h>
 #include <malloc.h>
 #include <spi.h>
 #include <asm/mpc8xxx_spi.h>
+#include <asm-generic/gpio.h>
 
 enum {
 	SPI_EV_NE = BIT(31 - 22),	/* Receiver Not Empty */
@@ -30,6 +32,12 @@
 	SPI_COM_LST = BIT(31 - 9),
 };
 
+struct mpc8xxx_priv {
+	spi8xxx_t *spi;
+	struct gpio_desc gpios[16];
+	int max_cs;
+};
+
 static inline u32 to_prescale_mod(u32 val)
 {
 	return (min(val, (u32)15) << 16);
@@ -42,70 +50,90 @@
 
 #define SPI_TIMEOUT	1000
 
-struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+static int __spi_set_speed(spi8xxx_t *spi, uint speed)
 {
-	struct spi_slave *slave;
+	/* TODO(mario.six@gdsys.cc): This only ever sets one fixed speed */
 
-	if (!spi_cs_is_valid(bus, cs))
-		return NULL;
+	/* Use SYSCLK / 8 (16.67MHz typ.) */
+	clrsetbits_be32(&spi->mode, SPI_MODE_PM_MASK, to_prescale_mod(1));
 
-	slave = spi_alloc_slave_base(bus, cs);
-	if (!slave)
-		return NULL;
-
-	/*
-	 * TODO: Some of the code in spi_init() should probably move
-	 * here, or into spi_claim_bus() below.
-	 */
-
-	return slave;
+	return 0;
 }
 
-void spi_free_slave(struct spi_slave *slave)
+static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev)
 {
-	free(slave);
+	struct mpc8xxx_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	priv->spi = (spi8xxx_t *)dev_read_addr(dev);
+
+	/* TODO(mario.six@gdsys.cc): Read clock and save the value */
+
+	ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
+					ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
+	if (ret < 0)
+		return -EINVAL;
+
+	priv->max_cs = ret;
+
+	return 0;
 }
 
-void spi_init(void)
+static int mpc8xxx_spi_probe(struct udevice *dev)
 {
-	spi8xxx_t *spi = &((immap_t *)(CONFIG_SYS_IMMR))->spi;
+	struct mpc8xxx_priv *priv = dev_get_priv(dev);
 
 	/*
 	 * SPI pins on the MPC83xx are not muxed, so all we do is initialize
 	 * some registers
 	 */
-	out_be32(&spi->mode, SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN);
-	/* Use SYSCLK / 8 (16.67MHz typ.) */
-	clrsetbits_be32(&spi->mode, SPI_MODE_PM_MASK, to_prescale_mod(1));
-	/* Clear all SPI events */
-	setbits_be32(&spi->event, 0xffffffff);
-	/* Mask  all SPI interrupts */
-	clrbits_be32(&spi->mask, 0xffffffff);
-	/* LST bit doesn't do anything, so disregard */
-	out_be32(&spi->com, 0);
-}
+	out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN);
 
-int spi_claim_bus(struct spi_slave *slave)
-{
+	__spi_set_speed(priv->spi, 16666667);
+
+	/* Clear all SPI events */
+	setbits_be32(&priv->spi->event, 0xffffffff);
+	/* Mask  all SPI interrupts */
+	clrbits_be32(&priv->spi->mask, 0xffffffff);
+	/* LST bit doesn't do anything, so disregard */
+	out_be32(&priv->spi->com, 0);
+
 	return 0;
 }
 
-void spi_release_bus(struct spi_slave *slave)
+static void mpc8xxx_spi_cs_activate(struct udevice *dev)
 {
+	struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
+	struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+
+	dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
+	dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
 }
 
-int spi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, void *din,
-	     ulong flags)
+static void mpc8xxx_spi_cs_deactivate(struct udevice *dev)
 {
-	spi8xxx_t *spi = &((immap_t *)(CONFIG_SYS_IMMR))->spi;
-	u32 tmpdin;
+	struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
+	struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+
+	dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
+	dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
+}
+
+static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,
+			    const void *dout, void *din, ulong flags)
+{
+	struct udevice *bus = dev->parent;
+	struct mpc8xxx_priv *priv = dev_get_priv(bus);
+	spi8xxx_t *spi = priv->spi;
+	struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+	u32 tmpdin = 0;
 	int num_blks = DIV_ROUND_UP(bitlen, 32);
 
-	debug("%s: slave %u:%u dout %08X din %08X bitlen %u\n", __func__,
-	      slave->bus, slave->cs, *(uint *)dout, *(uint *)din, bitlen);
+	debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__,
+	      bus->name, platdata->cs, *(uint *)dout, *(uint *)din, bitlen);
 
 	if (flags & SPI_XFER_BEGIN)
-		spi_cs_activate(slave);
+		mpc8xxx_spi_cs_activate(dev);
 
 	/* Clear all SPI events */
 	setbits_be32(&spi->event, 0xffffffff);
@@ -178,15 +206,57 @@
 			mdelay(1);
 		} while (get_timer(start) < SPI_TIMEOUT);
 
-		if (get_timer(start) >= SPI_TIMEOUT)
+		if (get_timer(start) >= SPI_TIMEOUT) {
 			debug("*** %s: Time out during SPI transfer\n",
 			      __func__);
+			return -ETIMEDOUT;
+		}
 
 		debug("*** %s: transfer ended. Value=%08x\n", __func__, tmpdin);
 	}
 
 	if (flags & SPI_XFER_END)
-		spi_cs_deactivate(slave);
+		mpc8xxx_spi_cs_deactivate(dev);
 
 	return 0;
 }
+
+static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed)
+{
+	struct mpc8xxx_priv *priv = dev_get_priv(dev);
+
+	return __spi_set_speed(priv->spi, speed);
+}
+
+static int mpc8xxx_spi_set_mode(struct udevice *dev, uint mode)
+{
+	/* TODO(mario.six@gdsys.cc): Using SPI_CPHA (for clock phase) and
+	 * SPI_CPOL (for clock polarity) should work
+	 */
+	return 0;
+}
+
+static const struct dm_spi_ops mpc8xxx_spi_ops = {
+	.xfer		= mpc8xxx_spi_xfer,
+	.set_speed	= mpc8xxx_spi_set_speed,
+	.set_mode	= mpc8xxx_spi_set_mode,
+	/*
+	 * cs_info is not needed, since we require all chip selects to be
+	 * in the device tree explicitly
+	 */
+};
+
+static const struct udevice_id mpc8xxx_spi_ids[] = {
+	{ .compatible = "fsl,spi" },
+	{ }
+};
+
+U_BOOT_DRIVER(mpc8xxx_spi) = {
+	.name	= "mpc8xxx_spi",
+	.id	= UCLASS_SPI,
+	.of_match = mpc8xxx_spi_ids,
+	.ops	= &mpc8xxx_spi_ops,
+	.ofdata_to_platdata = mpc8xxx_spi_ofdata_to_platdata,
+	.probe	= mpc8xxx_spi_probe,
+	.priv_auto_alloc_size = sizeof(struct mpc8xxx_priv),
+};